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ltc3862-2 1 38622f typical a pplica t ion fea t ures a pplica t ions descrip t ion multi-phase current mode step-up dc/dc controller the ltc ? 3862-2 is a two-phase constant frequency, current mode boost and sepic controller that drives n-channel power mosfets. two-phase operation reduces system filtering capacitance and inductance requirements. the operating frequency can be set with an external resistor over a 75khz to 500khz range and can be synchronized to an external clock using the internal pll. multiphase operation is possible using the sync input, the clkout output and the phasemode control pin allowing 2-, 3-, 4-, 6- or 12-phase operation. other features include an internal 10v ldo with under - voltage lockout protection for the gate drivers, a preci- sion run pin threshold with programmable hysteresis, soft-start and programmable leading edge blanking and maximum duty cycle. part number intv cc uv + uv C ltc3862 5v 3.3v 2.9v ltc3862-1 10v 7.5v 7.0v ltc3862-2 10v 4.4v 3.9v n wide v in range: 5.5v to 36v operation n 2-phase operation reduces input and output capacitance n fixed frequency, peak current mode control n internal 10v ldo regulator n lower uvlo thresholds allows the use of mosfets rated at 6v v gs n adjustable slope compensation gain n adjustable max duty cycle (up to 96%) n adjustable leading edge blanking n 1% internal voltage reference n programmable operating frequency with one external resistor (75khz to 500khz) n phase-lockable fixed frequency 50khz to 650khz n sync input and clkout for 2-, 3-, 4-, 6- or 12-phase operation (phasemode programmable) n 24-lead narrow ssop package n 5mm 5mm qfn package with 0.65mm lead pitch n 24-lead thermally enhanced tssop package n automotive, telecom and industrial power supplies efficiency vs output current l , lt, ltc, ltm, linear technology, the linear logo and polyphase are registered trademarks and no r sense and thinsot are trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 6144194, 6498466, 6611131. v in ltc3862-2 sgnd gate1 sense1 + run 100k 24.9k 110k 796k 12.4k 12.1k 220pf 0.0033 0.0033 16h 16h 22f 50v 210f 100v 0.1f 1nf 10nf 4.7f intv cc ss 3v8 ith fb v out 80v 7a (max) 38622 ta01a v in 6v to 32v blank freq sync pllfltr sense1 ? gate2 sense2 + sense2 ? pgnd clkout slope d max phasemode load current (ma) efficiency (%) 38622 ta01b 97 87 89 91 93 95 77 79 81 83 85 10 1000 100 10000 v in = 6v v in = 9v v in = 12v v in = 24v v out = 80v
ltc3862-2 2 38622f a bsolu t e maxi m u m r a t ings input supply voltage (v in ) ......................... C0 .3v to 40v intv cc voltage .......................................... C0 .3v to 11v intv cc ldo rms output current ......................... 50m a run voltage ................................................. C0.3v to 8v sync voltage ............................................... C 0.3v to 6v slope, phasemode, d max , blank voltage .......................................... C 0.3v to 3v8 sense1 + , sense1 C , sense2 + , sense2 C voltage ...................................... C 0.3v to v 3v8 (notes 1, 2) 1 2 3 4 5 6 7 8 9 10 11 12 top view fe package 24-lead plastic tssop 24 23 22 21 20 19 18 17 16 15 14 13 d max slope blank phasemode freq ss ith fb sgnd clkout sync pllfltr 3v8 sense1 + sense1 ? run v in intv cc gate1 pgnd gate2 nc sense2 ? sense2 + 25 pgnd t jmax = 150c, ja = 38c/w exposed pad (pin 25) is pgnd, must be soldered to pcb 1 2 3 4 5 6 7 8 9 10 11 12 top view gn package 24-lead narrow plastic ssop 24 23 22 21 20 19 18 17 16 15 14 13 d max slope blank phasemode freq ss ith fb sgnd clkout sync pllfltr 3v8 sense1 + sense1 ? run v in intv cc gate1 pgnd gate2 nc sense2 ? sense2 + t jmax = 150c, ja = 85c/w 24 23 22 21 20 19 7 8 9 top view 25 pgnd uh package 24-lead (5mm 5mm) plastic qfn 10 11 12 6 5 4 3 2 1 13 14 15 16 17 18 blank phasemode freq ss ith fb v in intv cc gate1 pgnd gate2 nc slope dmax 3v8 sense1 + sense1 ? run sgnd clkout sync pllfltr sense2 + sense2 ? t jmax = 150c, ja = 44c/w exposed pad (pin 25) is pgnd, must be soldered to pcb p in c on f igura t ion ss, pllfltr voltage ................................ C 0.3v to v 3v8 ith voltage ............................................... C0 .3v to 2.7v fb voltage .................................................. C 0.3v to 3v8 freq voltage ............................................ C0 .3v to 1.5v operating junction temperature range (notes 3, 4) lt c3862-2e ......................................... C4 0c to 85c lt c3862-2i ........................................ C 40c to 125c lt c3862-2h ....................................... C 40c to 150c storage temperature range .................. C 65c to 150c reflow peak body temperature ........................... 26 0c
ltc3862-2 3 38622f lead free finish tape and reel part marking* package description temperature range ltc3862efe-2#pbf ltc3862efe-2#trpbf ltc3862fe-2 24-lead plastic tssop C40c to 85c ltc3862ife-2#pbf ltc3862ife-2#trpbf ltc3862fe-2 24-lead plastic tssop C40c to 125c ltc3862hfe-2#pbf ltc3862hfe-2#trpbf ltc3862fe-2 24-lead plastic tssop C40c to 150c ltc3862egn-2#pbf ltc3862egn-2#trpbf ltc3862gn-2 24-lead plastic ssop C40c to 85c ltc3862ign-2#pbf ltc3862ign-2#trpbf ltc3862gn-2 24-lead plastic ssop C40c to 125c ltc3862hgn-2#pbf ltc3862hgn-2#trpbf ltc3862gn-2 24-lead plastic ssop C40c to 150c ltc3862euh-2#pbf ltc3862euh-2#trpbf 38622 24-lead (5mm 5mm) plastic qfn C40c to 85c ltc3862iuh-2#pbf ltc3862iuh-2#trpbf 38622 24-lead (5mm 5mm) plastic qfn C40c to 125c ltc3862huh-2#pbf ltc3862huh-2#trpbf 38622 24-lead (5mm 5mm) plastic qfn C40c to 150c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ o r d er i n f or m a t ion e lec t rical c harac t eris t ics (notes 2, 3) the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v in = 12v, run = 2v and ss = open, unless otherwise noted. symbol parameter conditions min typ max units supply input and intv cc linear regulator v in v in supply voltage range l 5.5 36 v i vin v in supply current normal mode, no switching shutdown (note 5) v run = 0v l l 1.8 30 3.0 80 ma a intv cc ldo regulator output voltage 9.5 10.0 10.5 v dv intvcc(line) line regulation 12v < v in < 36v 0.002 0.02 %/v dv intvcc(load) load regulation load = 0ma to 20ma C2 % v uvlo intv cc uvlo voltage rising intv cc falling intv cc 4.4 3.9 v v 3v8 ldo regulator output voltage 3.8 v switcher control loop v fb reference voltage v ith = 0.8v (note 6) e-grade (note 3) i-grade and h-grade (note 3) l l 1.210 1.199 1.223 1.223 1.235 1.248 v v dv fb /dv in feedback voltage v in line regulation v in = 5.5v to 36v (note 6) 0.002 0.01 %/v dv fb /dv ith feedback voltage load regulation v ith = 0.5v to 1.2v (note 6) 0.01 0.1 % g m transconductance amplifier gain v ith = 0.8v (note 6), ith pin load = 5a 660 mho f 0db error amplifier unity-gain crossover frequency (note 7) 1.8 mhz
ltc3862-2 4 38622f symbol parameter conditions min typ max units v ith error amplifier maximum output voltage (internally clamped) v fb = 1v, no load 2.7 v error amplifier minimum output voltage v fb = 1.5v, no load 50 mv i ith error amplifier output source current C30 a error amplifier output sink current 30 a i fb error amplifier input bias currents (note 6) C50 C200 na v ith(pskip) pulse skip mode operation ith pin voltage rising ith voltage (note 6) hysteresis 0.275 25 v mv i sense(on) sense pin current 0.01 2 a v sense(max) maximum current sense input threshold v slope = float, low duty cycle (note 3) l 68 65 75 75 82 85 mv mv v sense(match) ch1 to ch2 maximum current sense threshold matching v slope = float, low duty cycle (note 3) (v sense1 C v sense2 ) l C7 7 mv run/soft-start i run run source current v run = 0v v run = 1.5v C0.5 C5 a a v run high level run channel enable threshold 1.22 v v runhys run threshold hysteresis 80 mv i ss ss pull-up current v ss = 0v C5 a r ss ss pull-down resistance v run = 0v 10 k oscillator f osc oscillator frequency r freq = 45.6k r freq = 45.6k l 280 260 300 300 320 340 khz khz oscillator frequency range l 75 500 khz v freq nominal freq pin voltage r freq = 45.6k 1.223 v f sync sync minimum input frequency v sync = external clock l 50 khz sync maximum input frequency v sync = external clock l 650 khz v sync sync input threshold rising threshold 1.5 v i pllfltr phase detector sourcing output current f sync > f osc C15 a phase detector sinking output current f sync < f osc 15 a ch1-ch2 channel 1 to channel 2 phase relationship v phasemode = 0v v phasemode = float v phasemode = 3v8 180 180 120 deg deg deg ch1-clkout channel 1 to clkout phase relationship v phasemode = 0v v phasemode = float v phasemode = 3v8 90 60 240 deg deg deg d max maximum duty cycle v dmax = 0v (note 9) v dmax = float v dmax = 3v8 96 84 75 % % % elec t rical charac t eris t ics (notes 2, 3) the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v in = 12v, run = 2v and ss = open, unless otherwise noted.
ltc3862-2 5 38622f e lec t rical c harac t eris t ics (notes 2, 3) the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c. v in = 12v, run = 2v and ss = open, unless otherwise noted. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to ground unless otherwise specified. note 3: the ltc3862e-2 is guaranteed to meet performance specifications from 0c to 85c. specifications over the C40c to 85c operating temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3862i-2 is guaranteed over the full C40c to 125c operating temperature range and the ltc3862h-2 is guaranteed over the full C40c to 150c operating temperature range. high junction temperatures degrade operating lifetimes. operating lifetime is derated at junction temperatures greater than 125c. note 4: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 5: supply current in normal operation is dominated by the current needed to charge the external mosfet gates. this current will vary with supply voltage and the external mosfets used. note 6: the ic is tested in a feedback loop that adjusts v fb to achieve a specified error amplifier output voltage. note 7: guaranteed by design, not subject to test. note 8: the minimum on-time condition is specified for an inductor peak- to-peak ripple current = 30% (see minimum on-time considerations in the applications information section). note 9: the maximum duty cycle limit is derived from an internal clock that runs at 12 the programmed switching frequency. see the applications information section for additional information. symbol parameter conditions min typ max units t on(min)1 minimum on-time v blank = 0v (note 8) 210 ns t on(min)2 minimum on-time v blank = float (note 8) 290 ns t on(min)3 minimum on-time v blank = 3v8 (note 8) 375 ns gate driver r ds(on) driver pull-up r ds(on) 3 driver pull-down r ds(on) 0.9 overvoltage v fb(ov) v fb , overvoltage lockout threshold v fb(ov) C v fb(nom) in percent 8 10 12 %
ltc3862-2 6 38622f typical p er f or m ance c harac t eris t ics efficiency vs output current load step inductor current at light load quiescent current vs input voltage quiescent current vs temperature shutdown quiescent current vs input voltage shutdown quiescent current vs temperature load current (ma) efficiency (%) 38622 ta01b 97 87 89 91 93 95 77 79 81 83 85 10 1000 100 10000 v in = 6v v in = 9v v in = 12v v in = 24v v out = 80v 38622 g02 i load 1a/div 500ma to 1a i load1 2a/div i load2 2a/div v out 1v/div v in = 24v v out = 72v 400s/div 38622 g03 sw1 50v/div sw2 50v/div i l 1a/div i l 1a/div v in = 24v v out = 72v i load = 100ma 1s/div input voltage (v) 4 quiescent current (ma) 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 3632 38622 g04 2.4 2.0 1.6 1.2 0.8 0.4 0 8 12 16 20 2824 temperature (c) ?50 quiescent current (ma) 1.85 1.90 150 38622 g05 1.80 1.75 1.70 1.65 1.60 1.55 1.50 ?25 0 25 50 100 125 75 input voltage (v) 4 8 shutdown current (a) 40 50 36 38622 g06 30 20 10 0 12 16 20 24 3228 temperature (c) ?50 shutdown current (a) 30 40 50 25 75 150 38622 g07 20 10 0 ?25 0 50 100 125 v in = 12v intv cc line regulation intv cc load regulation input voltage (v) 4 8 intv cc voltage (v) 6 8 12 10 36 38622 g08 4 2 12 16 20 24 3228 intv cc load current (ma) 0 intv cc voltage (v) 10.00 10.05 10.10 50 38622 g09 9.95 9.90 10 20 4030
ltc3862-2 7 38622f typical p er f or m ance c harac t eris t ics intv cc vs temperature intv cc ldo dropout voltage vs load current, temperature intv cc uvlo threshold vs temperature feedback voltage vs temperature feedback voltage line regulation current sense threshold vs ith voltage current sense threshold vs temperature maximum current sense threshold vs duty cycle run threshold vs temperature temperature (c) ?50 intv cc voltage (v) 10.03 10.04 10.05 25 75 150 38622 g10 10.02 10.01 10.00 9.95 9.96 9.97 9.98 9.99 ?25 0 50 100 125 intv cc load (ma) 0 dropout voltage (mv) 800 1000 1400 1200 20 50 38622 g11 600 400 200 0 10 30 40 150c 85c 25c ?40c 125c temperature (c) ?50 intv cc voltage (v) 4.6 150 38622 g12 4.5 3.6 3.7 3.8 3.9 4.4 4.3 4.2 4.1 4.0 0 50 100 rising falling temperature (c) ?50 1.211 fb voltage (v) 1.215 1.219 1.223 1.227 1.235 ?25 0 25 50 38622 g13 75 100 125 150 1.231 1.213 1.217 1.221 1.225 1.233 1.229 input voltage (v) 1.220 fb voltage (v) 1.221 1.222 1.223 1.224 12 20 28 36 38622 g14 1.225 1.226 8 16 24 32 ith voltage (v) current sense threshold (mv) 50 60 70 38622 g15 30 0 0 0.4 0.8 1.2 1.6 2.0 2.4 80 40 20 10 temperature (c) ?50 70 current sense threshold (mv) 71 73 74 75 80 77 0 50 75 38622 g16 72 78 79 76 ?25 25 100 125 150 duty cycle (%) 0 30 maximum current sense threshold (mv) 35 45 50 55 80 65 20 5040 7060 38622 g17 40 70 75 60 10 30 80 90 100 slope = 0.625 slope = 1 slope = 1.66 temperature (c) ?50 1.10 run pin voltage (v) 1.15 1.20 1.25 1.30 ?25 0 25 50 38622 g18 75 on off 100 125 150
ltc3862-2 8 38622f typical p er f or m ance c harac t eris t ics run threshold vs input voltage run (off) source current vs temperature run source current vs input voltage run (on) source current vs temperature soft-start current vs soft-start voltage oscillator frequency vs temperature soft-start current vs temperature oscillator frequency vs input voltage r freq vs frequency input voltage (v) 0 1.0 run pin voltage (v) 1.1 1.2 1.3 1.4 1.5 5 10 15 20 38622 g19 25 on off 30 35 40 temperature (c) ?50 ?1.0 run pin current (a) ?0.9 ?0.7 ?0.6 ?0.5 0 ?0.3 0 50 75 38622 g20 ?0.8 ?0.2 ?0.1 ?0.4 ?25 25 100 125 150 temperature (c) ?50 run pin current (a) ?4 ?2 150 38622 g21 ?6 ?8 0 50 100 ?25 25 75 125 0 ?5 ?3 ?7 ?1 input voltage (v) 4 run pin current (a) ?3 ?2 ?1 0 16 24 36 38622 g19 ?4 ?5 ?6 8 12 20 28 32 temperature (c) ?50 ?5.6 soft-start current (a) ?5.5 ?5.4 ?5.3 ?5.2 0 50 100 150 38622 g23 ?5.1 ?5.0 ?25 25 75 125 soft-start voltage (v) 0 ?6 soft-start current (a) ?5 ?4 ?3 ?2 1 2 3 4 38622 g24 ?1 0 0.5 1.5 2.5 3.5 temperature (c) ?50 frequency (khz) 302 303 304 305 150 38622 g25 301 300 298 0 50 100 ?25 25 75 125 299 307 306 input voltage (v) 4 8 frequency (khz) 300 305 310 315 36 38622 g26 295 290 280 12 20 28 16 24 32 285 320 frequency (khz) 100 r freq (k) 300 1000 38622 g27 10 100 200 1000 900 800700600 500 400 0
ltc3862-2 9 38622f typical p er f or m ance c harac t eris t ics frequency vs pllfltr voltage frequency pin voltage vs temperature minimum on-time vs input voltage minimum on-time vs temperature gate turn-on waveform driving renesas hat2267h gate turn-off waveform driving renesas hat2267h pllfltr voltage (v) 0 1000 1200 1400 2 38622 g28 800 600 0.5 1 1.5 2.5 400 200 0 frequency (khz) temperature (c) ?50 freq voltage (v) 1.223 1.229 1.231 150 38622 g29 1.221 1.219 1.211 0 50 100 ?25 25 75 125 1.215 1.235 1.233 1.227 1.225 1.217 1.213 temperature (c) ?50 130 minimum on-time (ns) 180 230 280 330 0 50 100 150 38622 g30 380 430 ?25 25 75 125 blank = 3v8 blank = float blank = sgnd input voltage (v) 4 8 130 minimum on-time (ns) 180 230 280 330 12 20 28 36 38622 g31 380 430 16 24 32 blank = 3v8 blank = float blank = sgnd 38622 g32 20ns/div v gate 2v/div v in = 24v v out = 72v i load = 0.25a 38622 g33 20ns/div v gate 2v/div v in = 24v v out = 72v i load = 0.25a
ltc3862-2 10 38622f p in func t ions 3v8: output of the internal 3.8v ldo from intv cc . supply pin for the low voltage analog and digital circuits. a low esr 1nf ceramic bypass capacitor should be connected between 3v8 and sgnd, as close as possible to the ic. blank: blanking time. floating this pin provides a nominal minimum on-time of 290ns. connecting this pin to 3v8 provides a minimum on-time of 375ns, while connecting it to sgnd provides a minimum on-time of 210ns. clkout: digital output used for daisy-chaining multiple ltc3862-2 ics in multi-phase systems. the phasemode pin voltage controls the relationship between ch1 and ch2 as well as between ch1 and clkout. d max : maximum duty cycle. this pin programs the maximum duty cycle. floating this pin provides 84% duty cycle. connecting this pin to 3v8 provides 75% duty cycle, while connecting it to sgnd provides 96% duty cycle. the maximum duty cycle limit is derived from an internal clock that runs at 12 the programmed switching frequency. as a result, the maximum duty cycle limit d max is extremely precise. fb: error amplifier input. the fb pin should be connected through a resistive divider network to v out to set the output voltage. freq: a resistor from freq to sgnd sets the operating frequency. gate1, gate2: gate drive output. the ltc3862-2 pro - vides a 10v gate drive referenced to pgnd to drive a high voltage mosfet. intv cc : output of the internal 10v low dropout regulator (ldo). a low esr 4.7f (x5r or better) ceramic bypass capacitor should be connected between intv cc and pgnd, as close as possible to the ic. ith: error amplifier output. the current comparator trip threshold increases with the ith control voltage. the ith pin is also used for compensating the control loop of the converter. pgnd: power ground. connect this pin close to the sources of the power mosfets. pgnd should also be connected to the negative terminals of v in and intv cc bypass capaci- tors. pgnd is electrically isolated from the sgnd pin. the exposed pad of the qfn and fe packages is connected to pgnd and must be soldered to pcb ground for electrical contact and rated thermal performance. phasemode: the phasemode pin voltage programs the phase relationship between ch1 and ch2 rising gate signals, as well as the phase relationship between ch1 gate signal and clkout. floating this pin or connecting it to either 3v8, or sgnd changes the phase relationship between ch1, ch2 and clkout. pllfltr: pll lowpass filter input. when synchronizing to an external clock, this pin serves as the lowpass filter input for the pll. a series resistor and capacitor connected from pllfltr to sgnd compensate the pll feedback loop. run: run control input. a voltage above 1.22v on the pin turns on the ic. forcing the pin below 1.22v causes the ic to shut down. there is a 0.5a pull-up current for this pin. once the run pin raises above 1.22v, an additional 4.5a pull-up current is added to the pin for program - mable hysteresis.
ltc3862-2 11 38622f p in func t ions sense1 + , sense2 + : positive inputs to the current comparators. the ith pin voltage programs the current comparator offset in order to set the peak current trip threshold. this pin is normally connected to a sense resistor in the source of the power mosfet. sense1 C , sense2 C : negative inputs to the current com- parators. this pin is normally connected to the bottom of the sense resistor. sgnd: signal ground. all feedback and soft-start connec- tions should return to sgnd. for optimum load regulation, the sgnd pin should be kelvin connected to the pcb location between the negative terminals of the output capacitors. slope: this pin programs the gain of the internal slope compensation. floating this pin provides a normalized slope compensation gain of 1.00. connecting this pin to 3v8 increases the normalized slope compensation by 66%, and connecting it to sgnd decreases the normal- ized slope compensation by 37.5%. see the applications information section for more details. ss: soft-start input. for soft-start operation, connecting a capacitor from this pin to sgnd will clamp the output of the error amp. an internal 5a current source will charge the capacitor and set the rate of increase of the peak switch current of the converter. sync: pll synchronization input. applying an external clock between 50khz and 650khz will cause the operating frequency to synchronize to the clock. sync is pulled down by a 50k internal resistor. the rising edge of the sync input waveform will align with the rising edge of gate1 in closed-loop operation. v in : main supply input. a low esr ceramic capacitor should be connected between this pin and sgnd.
ltc3862-2 12 38622f func t ional diagra m + d max phasemode freq slope r freq r c pllfltr sync clkout r p c p slope compensation sync detect blank ss 3v8 5a blogic blank logic logic over temp bias c ss c c clk1 clk2 d max ot ov ot uv sd 1.223v pskip pskip 0.275v pskip itrip uv vco pwm latch s r1 q ot uvlo 3.8v ldo 10v ldo uv sd blogic r2 + ? + ? icmp r loop v to i ith run ? + ov ov 1.345v + ? sd run 4.5a 1.22v + ? ea 0.5a sgnd v fb r1 38622 fd gate 3v8 intv cc v in v in pgnd sense + sense ? duplicate for second channel c vcc c in c out v out c 3v8 m d l r2 r s
ltc3862-2 13 38622f o pera t ion the control loop the ltc3862-2 uses a constant frequency, peak current mode step-up architecture with its two channels operat - ing 180 degrees out-of-phase. during normal operation, each external mosfet is turned on when the clock for that channel sets the pwm latch, and is turned off when the main current comparator, icmp, resets the latch. the peak inductor current at which icmp trips and resets the latch is controlled by the voltage on the ith pin, which is the output of the error amplifier, ea. the error amplifier compares the output feedback signal at the v fb pin to the internal 1.223v reference and generates an error signal at the ith pin. when the load current increases it causes a slight decrease in v fb relative to the reference voltage, which causes the ea to increase the ith voltage until the average inductor current matches the new load current. after the mosfet is turned off, the inductor current flows through the boost diode into the output capacitor and load, until the beginning of the next clock cycle. cascaded ldos supply power to the gate driver and control circuitry the ltc3862-2 contains two cascaded pmos output stage low dropout voltage regulators (ldos), one for the gate drive supply (intv cc ) and one for the low voltage analog and digital control circuitry (3v8). a block diagram of this power supply arrangement is shown in figure 1. the gate driver supply ldo (intv cc ) the 10v output (intv cc ) of the first ldo is powered from v in and supplies power to the power mosfet gate driv- ers. the intv cc pin should be bypassed to pgnd with a minimum of 4.7f of ceramic capacitance (x5r or better), placed as close as possible to the ic pins. if two power mosfets are connected in parallel for each channel in order to increase the output power level, or if a single mosfet with a q g greater than 50nc is used, then it is recommended that the bypass capacitance be increased to a minimum of 10f. an undervoltage lockout (uvlo) circuit senses the intv cc regulator output in order to protect the power mosfets from operating with inadequate gate drive. for the ltc3862-2 the rising uvlo threshold is typically 4.4v and the hys- teresis is typically 500mv. the ltc3862-2 was optimized for high voltage power mosfets with r ds(on) ratings at a v gs of 6v. for applications requiring logic-level power mosfets, please refer to the ltc3862 data sheet. figure 1. cascaded ldos provide gate drive and control circuitry power ? + sgnd r2 r1 1.223v ltc3862-2 intv cc 3v8 gate ? + sgnd r4 r3 1.223v p-ch p-ch analog circuits logic intv cc v in c in c vcc c 3v8 38622 f01 pgnd 3v8 sgnd note: place c vcc and c 3v8 capacitors as close as possible to device pins
ltc3862-2 14 38622f o pera t ion in multi-phase applications, all of the fb pins are connected together and all of the error amplifier output pins (ith) are connected together. the intv cc pins, however, should not be connected together. the intv cc regulator is capable of sourcing current but is not capable of sinking current. as a result, when two or more intv cc regulator outputs are connected together, the highest voltage regulator supplies all of the gate drive and control circuit current, and the other regulators are off. this would place a thermal burden on the highest output voltage ldo and could cause the maximum die temperature to be exceeded. in multi-phase ltc3862-2 applications, each intv cc regulator output should be independently bypassed to its respective pgnd pin as close as possible to each ic. the low voltage analog and digital supply ldo (3v8) the second ldo within the ltc3862-2 is powered off of intv cc and serves as the supply to the low voltage analog and digital control circuitry, as shown in figure 1. the output voltage of this ldo (which also has a pmos output device) is 3.8v. most of the analog and digital con - trol circuitry is powered from the internal 3v8 ldo. the 3v8 pin should be bypassed to sgnd with a 1nf ceramic capacitor (x5r or better), placed as close as possible to the ic pins. this ldo is not intended to be used as a supply for external circuitry. thermal considerations and package options the ltc3862-2 is offered in three package options. the 5mm 5mm qfn package (uh24) has a thermal resistance r th(ja) of 34c/w, the 24-pin tssop (fe24) package has a thermal resistance of 38c/w, and the 24-pin ssop (gn24) package has a thermal resistance of 85c/w. the qfn and tssop package options have a lead pitch of 0.65mm, and the gn24 option has a lead pitch of 0.025in. the intv cc regulator can supply up to 50ma of total current. as a result, care must be taken to ensure that the maximum junction temperature of the ic is never exceeded. the junction temperature can be estimated using the following equations: i q(tot) = i q + q g(tot) ? f p diss = v in ? (i q + q g(tot) ? f) t j = t a + p diss ? r th(ja) the total quiescent current (i q(tot) ) consists of the static supply current (i q ) and the current required to charge the gate capacitance of the power mosfets. the value of q g(tot) should come from the plot of v gs vs q g in the typical performance characteristics section of the mosfet data sheet. the value listed in the electrical specifications may be measured at a higher v gs , such as 15v, whereas the value of interest is at the 10v intv cc gate drive voltage. as an example of the required thermal analysis, consider a 2-phase boost converter with a 5.5v to 24v input voltage range and an output voltage of 72v at 1.5a. the switching frequency is 150khz and the maximum ambient tempera- ture is 70c. the power mosfet used for this application is the renesas hat2267h, which has a typical r ds(on) of 13m at v gs = 10v. from the plot of v gs vs q g , the total gate charge at v gs = 10v is 30nc (the temperature coef - ficient of the gate charge is low). one power mosfet is used for each phase. for the qfn package option: i q(tot) = 3ma + 2 ? 30nc ? 150khz = 12ma p diss = 24v ? 12ma = 288mw t j = 70c + 288mw ? 34c/w = 79.8c in this example, the junction temperature rise is only 9.8c. these equations demonstrate how the gate charge current typically dominates the quiescent current of the ic, and how the choice of package option and board heat sinking can have a significant effect on the thermal performance of the solution.
ltc3862-2 15 38622f o pera t ion to prevent the maximum junction temperature from be - ing exceeded, the input supply current to the ic should be checked when operating in continuous mode (heavy load) at maximum v in . a trade-off between the operat- ing frequency and the size of the power mosfets may need to be made in order to maintain a reliable junction temperature. finally, it is important to verify the calcula - tions by performing a thermal analysis of the final pcb using an infrared camera or thermal probe. as an option, an external regulator shown in figure 3 can be used to reduce the total power dissipation on the ic. thermal shutdown protection in the event of an overtemperature condition (external or internal), an internal thermal monitor will shut down the gate drivers and reset the soft-start capacitor if the die temperature exceeds 170c. this thermal sensor has a hysteresis of 10c to prevent erratic behavior at hot temperatures. the ltc3862-2s internal thermal sen - sor is intended to protect the device during momentary overtemperature conditions. continuous operation above the specified maximum operating junction temperature, however, may result in device degradation. operation at low supply voltage the ltc3862-2 has a minimum input voltage of 5.5v, making it a good choice for applications that require high voltage power mosfets with 6v r ds(on) ratings. the gate driver for the ltc3862-2 consists of pmos pull-up and nmos pull-down devices, allowing the full intv cc voltage to be applied to the gates during power mosfet switch- ing. nonetheless, care should be taken to determine the minimum gate drive supply voltage (intv cc ) in order to choose the optimum power mosfets. important param - eters that can affect the minimum gate drive voltage are the minimum input voltage (v in(min) ), the ldo dropout voltage, the q g of the power mosfets, and the operating frequency. if the input voltage v in is low enough for the intv cc ldo to be in dropout, then the minimum gate drive supply voltage is: v intvcc = v in(min) C v dropout the ldo dropout voltage is a function of the total gate drive current and the quiescent current of the ic (typically 3ma). a curve of dropout voltage vs output current for the ldo is shown in figure 2. the temperature coefficient of the ldo dropout voltage is approximately 6000ppm/c. the total q-current (i q(tot) ) flowing in the ldo is the sum of the controller quiescent current (3ma) and the total gate charge drive current. i q(tot) = i q + q g(tot) ? f after the calculations have been completed, it is impor - tant to measure the gate drive waveforms and the gate driver supply voltage (intv cc to pgnd) over all operating conditions (low v in , nominal v in and high v in , as well as from light load to full load) to ensure adequate power mosfet enhancement. consult the power mosfet data sheet to determine the actual r ds(on) for the measured v gs , and verify your thermal calculations by measuring the component temperatures using an infrared camera or thermal probe. figure 2. intv cc ldo dropout voltage vs current intv cc load (ma) 0 dropout voltage (mv) 800 1000 1400 1200 20 50 38622 f02 600 400 200 0 10 30 40 150c 85c 25c ?40c 125c
ltc3862-2 16 38622f o pera t ion operation at high supply voltage at high input voltages, the ltc3862-2s internal ldo can dissipate a significant amount of power, which could cause the maximum junction temperature to be exceeded. conditions such as a high operating frequency, or the use of more than one power mosfet per channel, could push the junction temperature rise to high levels. if the thermal equations above indicate too high a rise in the junction temperature, an external bias supply can always be used to reduce the power dissipation on the ic, as shown in figure 3. for example, a 12v system rail that is available would be more suitable than the 24v main input power rail to power the ltc3862-2. also, the bias power can be generated with a separate switching or ldo regulator. an example of an ldo regulator is shown in figure 3. the output voltage of the ldo regulator can be set by selecting an appropri- ate zener diode to be higher than 10v but low enough to divide the power dissipation between ltc3862-2 and q1 in figure 3. the absolute maximum voltage rating of the intv cc pin is 11v. supplies. independently biasing the intv cc pin from a separate power supply can cause one of two possible failure modes during supply sequencing. if the intv cc supply comes up before the v in supply, high current will flow from the external intv cc supply, through the body diode of the ldo pmos device, to the input capacitor and v in pin. this high current flow could trigger a latchup condition and cause catastrophic failure of the ic. if, however, the v in supply to the ic comes up before the intv cc supply, the external intv cc supply will act as a load to the internal ldo in the ltc3862-2, and the ldo will attempt to charge the intv cc output with its short-circuit current. this will result in excessive power dissipation and possible thermal overload of the ltc3862-2. programming the output voltage the output voltage is set by a resistor divider according to the following formula: v out = 1.223v 1 + r2 r1 ? ? ? ? ? ? the external resistor divider is connected to the output as shown in figure 4. resistor r1 is normally chosen so that the output voltage error caused by the current flowing out of the v fb pin during normal operation is negligible compared to the current in the divider. for an output volt - age error due to the error amp input bias current of less than 0.5%, this translates to a maximum value of r1 of about 30k. figure 3. using the ltc3862-2 with an external bias supply figure 4. programming the output voltage with a resistor divider power supply sequencing as shown in figure 1, there are body diodes in parallel with the pmos output transistors in the two ldo regulators in the ltc3862-2. as a result, it is not possible to bias the intv cc and v in pins of the chip from separate power v in r1 q1 d1 c vcc 38622 f03 ltc3862-2 v in intv cc ltc3862-2 fb sgnd r2 r1 38622 f04 v out
ltc3862-2 17 38622f o pera t ion operation of the run pin the control circuitry in the ltc3862-2 is turned on and off using the run pin. pulling the run pin below 1.22v forces shutdown mode and releasing it allows a 0.5a current source to pull this pin up, allowing a normally on converter to be designed. alternatively, the run pin can be externally pulled up or driven directly by logic. care must be taken not to exceed the absolute maximum rating of 8v for this pin. the comparator on the run pin can also be used to sense the input voltage, allowing an undervoltage detection circuit to be designed. this is helpful in boost converter applications where the input current can reach very high levels at low input voltage: i in = i out ? v out v in the 1.22v input threshold of the run comparator is derived from a precise bandgap reference, in order to maximize the accuracy of the undervoltage-sensing function. the run comparator has 80mv built-in hysteresis. when the voltage on the run pin exceeds 1.22v, the current sourced into the run pin is switched from 0.5a to 5a ptat (proportional to absolute temperature) current. the user can therefore program both the rising threshold and the amount of hysteresis using the values of the resistors in the external divider, as shown in the following equations: v in(on) = 1.22v 1 + r a r b ? ? ? ? ? ? C 0.5 ? r a v in(off) = 1.22v 1 + r a r b ? ? ? ? ? ? C 5 ? r a several of the possible run pin control techniques are illustrated in figure 5. frequency selection and the phase-locked loop the selection of the switching frequency is a trade-off between efficiency and component size. low frequency operation increases efficiency by reducing mosfet switching losses, but requires a larger inductor and output capacitor to maintain low output ripple. figure 5a. using the run pin for a normally on converter figure 5b. on/off control using external logic figure 5c. programming the input voltage turn-on and turn-off thresholds using the run pin ? + run comparator 1.22v 38622 f05a v in ltc3862-2 run 10v internal 5v 0.5a 4.5a sgnd bias and start-up control ? + run comparator 1.22v 38622 f05b v in ltc3862-2 run 10v internal 5v external logic control 0.5a 4.5a sgnd bias and start-up control ? + run comparator 1.22v 38622 f05c v in ltc3862-2 run 10v internal 5v 0.5a r a 4.5a sgnd bias and start-up control r b
ltc3862-2 18 38622f o pera t ion the ltc3862-2 uses a constant frequency architecture that can be programmed over a 75khz to 500khz range using a single resistor from the freq pin to ground. figure 6 illustrates the relationship between the freq pin resistance and the operating frequency. the operating frequency of the ltc3862-2 can be ap - proximated using the following formula: r freq = 5.5096e9(f osc ) C0.9255 a phase-lock loop is available on the ltc3862-2 to syn - chronize the internal oscillator to an external clock source connected to the sync pin. connect a series rc network from the pllfltr pin to sgnd to compensate plls feedback loop. typical compensation components are a 0.01f capacitor in series with a 10k resistor. the pllfltr pin is both the output of the phase detector and the input to the voltage controlled oscillator (vco). the ltc3862-2 phase detector adjusts the voltage on the pllfltr pin to align the rising edge of gate1 to the leading edge of the external clock signal, as shown in figure 7. the ris- ing edge of gate2 will depend upon the voltage on the phasemode pin. the capture range of the ltc3862-2s pll is 50khz to 650khz. because the operating frequency of the ltc3862-2 can be programmed using an external resistor, in synchronized applications, it is recommended that the free-running fre- quency (as defined by the external resistor) be set to the same value as the synchronized frequency. this results in a start-up of the ic at approximately the same frequency as the external clock, so that when the sync signal comes alive, no discontinuity at the output will be observed. it also ensures that the operating frequency remains essentially constant in the event the sync signal is lost. the sync pin has an internal 50k resistor to ground. using the clkout and phasemode pins in multi-phase applications the ltc3862-2 features two pins (clkout and phase - mode) that allow multiple ics to be daisy-chained together for higher current multi-phase applications. for a 3- or 4 - phase design, the clkout signal of the master controller is connected to the sync input of the slave controller in order to synchronize additional power stages for a single figure 6. freq pin resistor value vs frequency figure 7. synchronization of the ltc3862-2 to an external clock using the pll high current output. the phasemode pin is used to adjust the phase relationship between channel 1 and channel 2, as well as the phase relationship between channel 1 and clkout, as summarized in table 1. the phases are cal - culated relative to the zero degrees, defined as the rising edge of the gate1 output. in a 6-phase application the clkout pin of the master controller connects to the sync input of the 2nd controller and the clkout pin of the 2nd controller connects to the sync pin of the 3rd controller. table 1 phasemode ch-1 to ch-2 phase ch-1 to clkout phase application sgnd 180 90 2-phase, 4-phase float 180 60 6-phase 3v8 120 240 3-phase frequency (khz) 100 r freq (k) 300 1000 38622 f06 10 100 200 1000 900 800700600 500 400 0 sync 10v/div gate1 20v/div gate2 20v/div clkout 10v/div 2s/div v in = 24v v out = 72v i out = 0.5a phasemode = sgnd 38622 f07
ltc3862-2 19 38622f o pera t ion using the ltc3862-2 transconductance (g m ) error amplifier in multi-phase applications the ltc3862-2 error amplifier is a transconductance, or g m amplifier, meaning that it has high dc gain but high output impedance (the output of the error amplifier is a current proportional to the differential input voltage). this style of error amplifier greatly eases the task of implementing a multi-phase solution, because the amplifiers from two or more chips can be connected in parallel. in this case the fb pins of multiple ltc3862-2s can be connected to - gether, as well as the ith pins, as shown in figure 8. the g m of the composite error amplifier is simply n times the transconductance of one amplifier, or g m(tot) = n ? 660s, where n is the number of amplifiers connected in paral- lel. the transfer function from the ith pin to the current comparator inputs was carefully designed to be accurate, both from channel-to-channel and chip-to-chip. this way the peak inductor current matching is kept accurate. a buffered version of the output of the error amplifier deter - mines the threshold at the input of the current comparator. the ith voltage that represents zero peak current is 0.4v and the voltage that represents current limit is 1.2v (at low duty cycle). during an overload condition, the output of the error amplifier is clamped to 2.6v at low duty cycle, in order to reduce the latency when the overload condition terminates. a patented circuit in the ltc3862-2 is used to recover the slope compensation signal, so that the maximum peak inductor current is not a strong function of the duty cycle. in multi-phase applications that use more than one ltc3862-2 controller, it is possible for ground currents on the pcb to disturb the control lines between the ics, resulting in erratic behavior. in these applications the fb pins should be connected to each other through 100? resistors and each slave fb pin should be decoupled locally with a 100pf capacitor to ground, as shown in figure 8. soft-start the start-up of the ltc3862-2 is controlled by the volt - age on the ss pin. an internal pnp transistor clamps the current comparator sense threshold during soft-start, thereby limiting the peak switch current. the base of the pnp is connected to the ss pin and the emitter to an figure 8. ltc3862-2 error amplifier configuration for multi-phase operation internal, buffered ith node (please note that the ith pin voltage may not track the soft-start voltage during this time period). an internal 5a current source charges the ss capacitor, and clamps the peak sense threshold until the voltage on the soft-start capacitor reaches approximately 0.6v. the required amount of soft-start capacitance can be estimated using the following equation: c ss = 5a t ss 0.6v ? ? ? ? ? ? the ss pin has an internal open-drain nmos pull-down transistor that turns on when the run pin is pulled low, when the voltage on the intv cc pin is below its under - voltage lockout threshold, or during an overtemperature condition. in multi-phase applications that use more than freq fb clkout sync pllfltr ltc3862-2 master sgnd ith v out intv cc ss phasemode run on/off control all run pins connnected together individual intv cc pins locally decoupled freq fb ? ? clkout sync pllfltr ltc3862-2 slave sgnd ith intv cc ss run slave 38622 f08 all ss pins connnected together ** fb all fb pins connected together all ith pins connected together clkout * r = 100 ? c x = 100pf sync pllfltr ltc3862-2 sgnd ith intv cc ss run ** phasemode phasemode ? ? ?
ltc3862-2 20 38622f o pera t ion one ltc3862-2 chip, connect all of the ss pins together and use one external capacitor to program the soft-start time. in this case, the current into the soft-start capaci - tor will be i ss = n ? 5a, where n is the number of ss pins connected together. figure 9 illustrates the start-up waveforms for a 2-phase ltc3862-2 application. an excessively large inductor would result in too much effective slope compensation, and the converter could become unstable. likewise, if too small an inductor were used, the internal ramp compensation could be inadequate to prevent subharmonic oscillation. the ltc3862-2 contains a pin that allows the user to program the slope compensation gain in order to opti- mize performance for a wider range of inductance. with the slope pin left floating, the normalized slope gain is 1.00. connecting the slope pin to ground reduces the normalized gain to 0.625 and connecting this pin to the 3v8 supply increases the normalized slope gain to 1.66. with the normalized slope compensation gain set to 1.00, the design equations assume an inductor ripple current of 20% to 40%, as with previous designs. depending upon the application circuit, however, a normalized gain of 1.00 may not be optimum for the inductor chosen. if the ripple current in the inductor is greater than 40%, the normalized slope gain can be increased to 1.66 (an increase of 66%) by connecting the slope pin to the 3v8 supply. if the inductor ripple current is less than 20%, the normalized slope gain can be reduced to 0.625 (a decrease of 37.5%) by connecting the slope pin to sgnd. to check the effectiveness of the slope compensation, apply a load step to the output and monitor the cycle-by-cycle behavior of the inductor current during the leading and trailing edges of the load current. vary the input voltage over its full range and check for signs of cycle-by-cycle sw node instability or subharmonic oscillation. when the figure 9. typical start-up waveforms for a boost converter using the ltc3862-2 figure 10. light load switching waveforms for the ltc3862-2 at the onset of pulse-skipping pulse-skipping operation at light load as the load current is decreased, the controller enters discontinuous mode (dcm). the peak inductor current can be reduced until the minimum on-time of the controller is reached. any further decrease in the load current will cause pulse-skipping to occur, in order to maintain output regulation, which is normal. the minimum on-time of the controller in this mode is approximately 210ns (with the blanking time set to its minimum value), the majority of which is leading edge blanking. figure 10 illustrates the ltc3862-2 switching waveforms at the onset of pulse- skipping. programmable slope compensation for a current mode boost regulator operating in ccm, slope compensation must be added for duty cycles above 50%, in order to avoid subharmonic oscillation. for the ltc3862-2, this ramp compensation is internal and user adjustable. having an internally fixed ramp compensation waveform normally places some constraints on the value of the inductor and the operating frequency. for example, with a fixed amount of internal slope compensation, using run 5v/div v out 100v/div i l1 2a/div i l2 2a/div 1ms/div v in = 24v v out = 72v r l = 100 38622 f09 sw1 50v/div sw2 50v/div i l1 500ma/div i l2 500ma/div 2s/div 38622 f10 v in = 51v v out = 72v light load (10ma)
ltc3862-2 21 38622f o pera t ion figure 12. effect of slope gain on the peak sense threshold slope compensation is too low the converter can suffer from excessive jitter or, worst case, subharmonic oscil - lation. when excess slope compensation is applied to the internal current sense signal, the phase margin of the control loop suffers. figure 11 illustrates inductor current waveforms for a properly compensated loop. the ltc3862-2 contains a patented circuit whereby most of the applied slope compensation is recovered, in order to provide a sense + to sense C threshold which is not a strong function of the duty cycle. this sense threshold is, however, a function of the programmed slope gain, as shown in figure 12. the data sheet typical specification of 75mv for sense + minus sense C is measured at a normal- ized slope gain of 1.00 at low duty cycle. for applications where the normalized slope gain is not 1.00, use figure 12 to determine the correct value of the sense resistor. programmable blanking and the minimum on-t ime the blank pin on the ltc3862-2 allows the user to program the amount of leading edge blanking at the sense pins. connecting the blank pin to sgnd results in a minimum on-time of 210ns, floating the pin increases this time to 290ns, and connecting the blank pin to the 3v8 supply results in a minimum on-time of 375ns. the majority of the minimum on-time consists of this leading edge blanking, due to the inherently low propagation delay of the current comparator (25ns typ) and logic circuitry (10ns to 15ns). the purpose of leading edge blanking is to filter out noise on the sense pins at the leading edge of the power mosfet turn-on. during the turn-on of the power mosfet the gate drive current, the discharge of any parasitic capacitance on the sw node, the recovery of the boost diode charge, and parasitic series inductance in the high di/dt path all contribute to overshoot and high frequency noise that could cause false-tripping of the current comparator. due to the wide range of applications the ltc3862-2 is well-suited to, fixing one value of the internal leading edge blanking time would have required the longest delay time to have been used. providing a means to program the blank time allows users to optimize the sense pin filtering for each application. figure 13 illustrates the effect of the program- mable leading edge blank time on the minimum on-time of a boost converter. programmable maximum duty cycle in order to maintain constant frequency and a low output ripple voltage, a single-ended boost (or flyback or sepic) converter is required to turn off the switch every cycle for some minimum amount of time. this off-time allows the transfer of energy from the inductor to the output capacitor and load, and prevents excessive ripple current and voltage. for inductor-based topologies like boost and sepic converters, having a maximum duty cycle as close as possible to 100% may be desirable, especially in low v in to high v out applications. however, for transformer- based solutions, having a maximum duty cycle near 100% is undesirable, due to the need for v ? sec reset during the primary switch off-time. figure 11. inductor current waveforms for a properly compensated control loop i load 1a/div v out 2v/div i l1 1a/div i l2 1a/div 20s/div 38622 f11 v in = 24v v out = 72v duty cycle (%) 30 maximum current sense threshold (mv) 60 70 80 55 50 45 40 35 65 75 20 40 60 80 38622 f12 100 100 30 50 70 90 slope = 0.625 slope = 1 slope = 1.66
ltc3862-2 22 38622f o pera t ion figure 13. leading edge blanking effects on the minimum on-time figure 14. sw node waveforms with different duty cycle limits in order to satisfy these different applications require- ments, the ltc3862-2 has a simple way to program the maximum duty cycle. connecting the d max pin to sgnd limits the maximum duty cycle to 96%. floating this pin limits the duty cycle to 84% and connecting the d max pin to the 3v8 supply limits it to 75%. figure 14 illustrates the effect of limiting the maximum duty cycle on the sw node waveform of a boost converter. the ltc3862-2 contains an oscillator that runs at 12 the programmed switching frequency, in order to provide for 2-, 3-, 4-, 6- and 12-phase operation. a digital counter is used to divide down the fundamental oscillator frequency in order to obtain the operating frequency of the gate drivers. since the maximum duty cycle limit is obtained from this digital counter, the percentage maximum duty cycle does not vary with process tolerances or temperature. sw node 20v/div gate 5v/div 500ns/div minimum on-time at light load with blank = sgnd v in = 36v v out = 72v measured on-time = 210ns v in = 36v v out = 72v measured on-time = 290ns v in = 36v v out = 72v measured on-time = 375ns inductor current 200ma/div sw node 20v/div gate 5v/div inductor current 200ma/div sw node 20v/div gate 5v/div inductor current 200ma/div 500ns/div minimum on-time at light load with blank = float 500ns/div 38622 f13 minimum on-time at light load with blank = 3v8 sw node 20v/div sw node 20v/div 1s/div 96% maximum duty cycle with d max = sgnd inductor current 1a/div 1s/div 84% maximum duty cycle with d max = float inductor current 1a/div sw node 20v/div inductor current 1a/div 1s/div 38622 f14 75% maximum duty cycle with d max = 3v8
ltc3862-2 23 38622f the sense + and sense C pins the sense + and sense C pins are high impedance inputs to the cmos current comparators for each channel. nominally, there is no dc current into or out of these pins. there are esd protection diodes connected from these pins to sgnd, although even at hot temperature the leakage current into the sense + and sense C pins should be less than 1a. since the ltc3862-2 contains leading edge blanking, an external rc filter is not required for proper operation. however, if an external filter is used, the filter components should be placed close to the sense + and sense C pins on the ic, as shown in figure 15. the positive and negative sense node traces should then run parallel to each other to a kelvin connection underneath the sense resistor, as shown in figure 16. sensing current elsewhere on the board can add parasitic inductance and capacitance to the current sense element, degrading the information at the sense pins and making the programmed current limit unpredictable. avoid the temptation to connect the sense C line to the ground plane using a pcb via; this could result in unpredictable behavior. the sense resistor should be connected to the source of the power mosfet and the ground node using short, wide pcb traces, as shown in figure 16. ideally, the bot - tom terminal of the sense resistors will be immediately figure 16. connecting the sense + and sense C traces to the sense resistor using a kelvin connection adjacent to the negative terminal of the output capacitor, since this path is a part of the high di/dt loop formed by the switch, boost diode, output capacitor and sense resis- tor. placement of the inductors is less critical, since the current in the inductors is a triangle waveform. checking the load transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to ?i load (esr), where esr is the effective series resistance of c out . ?i load also begins to charge or discharge c out , generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. the availability of the ith pin not only allows optimization of control loop behavior but also provides a dc-coupled and ac-filtered closed-loop response test point. the dc step, rise time and settling at this test point truly reflects the closed-loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. o pera t ion figure 15. proper current sense filter component placement sense ? sense + ltc3862-2 gate v out r sense 38622 f15 filter components placed near sense pins v in pgnd intv cc v in mosfet source to sense filter next to controller r sense gnd 38622 f16
ltc3862-2 24 38622f o pera t ion figure 17. load step response of a properly compensated boost converter the ith series r c ? c c filter sets the dominant pole-zero loop compensation. the transfer function for boost and flyback converters contains a right half plane zero that normally requires the loop crossover frequency to be reduced significantly in order to maintain good phase margin. the r c ? c c filter values can typically be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final pc layout is done and the particular output capacitor type(s) and value(s) have been determined. the output capacitor configuration needs to be selected in advance because the effective esr and bulk capacitance have a significant effect on the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1s to 10s will produce output voltage and ith pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. placing a power mosfet and load resistor directly across the output capacitor and driving the gate with an appropriate signal generator is a practi- cal way to produce a fast load step condition. the initial output voltage step resulting from the step change in the output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the ith pin signal which is in the feedback loop and is the filtered and compensated control loop response. the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. figure 17 illustrates the load step response of a properly compensated boost converter. i load 1a/div 500ma to 1a v out 1v/div i l1 2a/div i l2 2a/div 400s/div 38622 f17 v in = 24v v out = 72v
ltc3862-2 25 38622f figure 18. a typical 2-phase, single output boost converter application circuit typical boost applications circuit a basic 2-phase, single output ltc3862-2 application circuit is shown in figure 18. external component selec - tion is driven by the characteristics of the load and the input supply. duty cycle considerations for a boost converter operating in a continuous conduc- tion mode (ccm), the duty cycle of the main switch is: d = v o + v f C v in v o + v f ? ? ? ? ? ? = t on ? f where v f is the forward voltage of the boost diode. the minimum on-time for a given application operating in ccm is: t on(min) = 1 f v o + v f C v in(max) v o + v f ? ? ? ? ? ? for a given input voltage range and output voltage, it is important to know how close the minimum on-time of the application comes to the minimum on-time of the control ic. the ltc3862-2 minimum on-time can be programmed from 210ns to 375ns using the blank pin. minimum on-time limitations in a single-ended boost converter, two steady-state condi - tions can result in operation at the minimum on-time of the controller. the first condition is when the input voltage is close to the output voltage. when v in approaches v out the voltage across the inductor approaches zero during the switch off-time. under this operating condition the converter can become unstable and the output can experi- ence high ripple voltage oscillation at audible frequencies. for applications where the input voltage can approach or exceed the output voltage, consider using a sepic or buck-boost topology instead of a boost converter. the second condition that can result in operation at the minimum on-time of the controller is at light load, in deep discontinuous mode. as the load current is decreased, the on-time of the switch decreases, until the minimum on-time limit of the controller is reached. any further de- crease in the output current will result in pulse-skipping, a typically benign condition where cycles are skipped in order to maintain output regulation. a pplica t ions i n f or m a t ion sense1 + 3v8 slope blank clkout sync pllfltr phasemode d max 10nf sense1 ? sense2 ? sense2 + run freq ss v in 66.5k 24.9k 150k v in 8.5v to 36v d1 pds760 d2 pds760 10 l2 19h pa2050-193 ith sgnd v out 12.4k fb 39.2k 475k 0.1f 1f 1nf 6.8f 50v 0.005 1w q1 hat2279h q2 hat2279h 0.005 1w v out 48v 3a to 5a 38622 f18 100f 63v 100f 63v 6.8f 50v 6.8f 50v 6.8f 50v ltc3862-2 10nf 100pf intv cc gate1 gate2 pgnd 4.7f 10nf 6.8f 50v 6.8f 50v 6.8f 50v l1 19h pa2050-193 10 + +
ltc3862-2 26 38622f a pplica t ions i n f or m a t ion maximum duty cycle limitations another operating extreme occurs at high duty cycle, when the input voltage is low and the output voltage is high. in this case: d max = v o + v f C v in(min) v o + v f ? ? ? ? ? ? a single-ended boost converter needs a minimum off-time every cycle in order to allow energy transfer from the input inductor to the output capacitor. this minimum off-time translates to a maximum duty cycle for the converter. the equation above can be rearranged to obtain the maximum output voltage for a given minimum input or maximum duty cycle. v o(max) = v in 1C d max C v f the equation for d max above can be used as an initial guideline for determining the maximum duty cycle of the application circuit. however, losses in the inductor, input and output capacitors, the power mosfets, the sense resistors and the controller (gate drive losses) all contribute to an increasing of the duty cycle. the effect of these losses will be to decrease the maximum output voltage for a given minimum input voltage. after the initial calculations have been completed for an application circuit, it is important to build a prototype of the circuit and measure it over the entire input voltage range, from light load to full load, and over temperature, in order to verify proper operation of the circuit. peak and average input currents the control circuit in the ltc3862-2 measures the input current (by means of resistors in the sources of the power mosfets), so the output current needs to be reflected back to the input in order to dimension the power mosfets properly. based on the fact that, ideally, the output power is equal to the input power, the maximum average input current is: i in(max) = i o(max) 1C d max the peak current in each inductor is: i in(pk) = 1 n ? 1 + 2 ? ? ? ? ? ? ? i o(max) 1C d max where n represents the number of phases and represents the percentage peak-to-peak ripple current in the inductor. for example, if the design goal is to have 30% ripple cur - rent in the inductor, then = 0.30, and the peak current is 15% greater than the average. inductor selection given an input voltage range, operating frequency and ripple current, the inductor value can be determined using the following equation: l = v in(min) ? i l ? f ? d max where: ? i l = n ? i o(max) 1C d max choosing a larger value of ?i l allows the use of a lower value inductor but results in higher output voltage ripple, greater core losses, and higher ripple current ratings for the input and output capacitors. a reasonable starting point is 30% ripple current in the inductor ( = 0.3), or: ? i l = 0.3 n ? i o(max) 1C d max
ltc3862-2 27 38622f a pplica t ions i n f or m a t ion the inductor saturation current rating needs to be higher than the worst-case peak inductor current during an overload condition. if i o(max) is the maximum rated load current, then the maximum current limit value (i o(cl) ) would normally be chosen to be some factor (e.g., 30%) greater than i o(max) . i o(cl) = 1.3 ? i o(max) reflecting this back to the input, where the current is be- ing measured, and accounting for the ripple current, gives a minimum saturation current rating for the inductor of: i l(sat) 1 n ? 1 + 2 ? ? ? ? ? ? ? 1.3 ? i o(max) 1C d max the saturation current rating for the inductor should be determined at the minimum input voltage (which results in the highest duty cycle and maximum input current), maximum output current and the maximum expected core temperature. the saturation current ratings for most commercially available inductors drop at high temperature. to verify safe operation, it is a good idea to characterize the inductors core/winding temperature under the fol - lowing conditions: 1) worst-case operating conditions, 2) maximum allowable ambient temperature and 3) with the power supply mounted in the final enclosure. thermal characterization can be done by placing a thermocouple in intimate contact with the winding/core structure, or by burying the thermocouple within the windings themselves. remember that a single-ended boost converter is not short-circuit protected, and that under a shorted output condition, the output current is limited only by the input supply capability. for applications requiring a step-up converter that is short-circuit protected, consider using a sepic or forward converter topology. power mosfet selection the peak-to-peak gate drive level is set by the intv cc voltage is 10v for the ltc3862-2 under normal operat - ing conditions. selection criteria for the power mosfets include the r ds(on) , gate charge q g , drain-to-source breakdown voltage bv dss , maximum continuous drain current i d(max) , and thermal resistances r th(ja) and r th(jc) both junction-to-ambient and junction-to-case. the gate driver for the ltc3862-2 consists of pmos pull- up and nmos pull-down devices, allowing the full intv cc voltage to be applied to the gates during power mosfet switching. nonetheless, care must be taken to ensure that the minimum gate drive voltage is still sufficient to full enhance the power mosfet. check the mosfet data sheet carefully to verify that the r ds(on) of the mosfet is specified for a voltage less than or equal to the nominal intv cc voltage of 10v. for applications that require a power mosfet rated at 5v, please refer to the ltc3862 data sheet. also pay close attention to the bv dss specifications for the mosfets relative to the maximum actual switch volt - age in the application. check the switching waveforms of the mosfet directly on the drain terminal using a single probe and a high bandwidth oscilloscope. ensure that the drain voltage ringing does not approach the bv dss of the mosfet. excessive ringing at high frequency is normally an indicator of too much series inductance in the high di/ dt current path that includes the mosfet, the boost diode, the output capacitor, the sense resistor and the pcb traces connecting these components. finally, check the mosfet manufacturers data sheet for an avalanche energy rating (eas). some mosfets are not rated for body diode avalanche and will fail catastrophi- cally if the v ds exceeds the device bv dss , even if only by a fraction of a volt. avalanche-rated mosfets are better able to sustain high frequency drain-to-source ringing near the device bv dss during the turn-off transition. calculating power mosfet switching and conduction losses and junction temperatures in order to calculate the junction temperature of the power mosfet, the power dissipated by the device must be known. this power dissipation is a function of the duty cycle, the load current and the junction temperature itself (due to the positive temperature coefficient of its r ds(on) ). as a result, some iterative calculation is normally required to determine a reasonably accurate value.
ltc3862-2 28 38622f the power dissipated by the mosfet in a multi-phase boost converter with n phases is: p fet = i o(max) n ? 1C d max ( ) ? ? ? ? ? ? 2 ? r ds(on) ? d max ? t + k ? v out 2 ? i o(max) n ? 1C d max ( ) ? c rss ? f the first term in the equation above represents the i 2 r losses in the device, and the second term, the switching losses. the constant, k = 1.7, is an empirical factor inversely related to the gate drive current and has the dimension of 1/current. the t term accounts for the temperature coefficient of the r ds(on) of the mosfet, which is typically 0.4%/oc. figure 19 illustrates the variation of normalized r ds(on) over temperature for a typical power mosfet. from a known power dissipated in the power mosfet, its junction temperature can be obtained using the following formula: t j = t a + p fet ? r th(ja) the r th(ja) to be used in this equation normally includes the r th(jc) for the device plus the thermal resistance from the case to the ambient temperature (r th(ca) ). this value of t j can then be compared to the original, assumed value used in the iterative calculation process. it is tempting to choose a power mosfet with a very low r ds(on) in order to reduce conduction losses. in doing so, however, the gate charge q g is usually significantly higher, which increases switching and gate drive losses. since the switching losses increase with the square of the output voltage, applications with a low output voltage generally have higher mosfet conduction losses, and high output voltage applications generally have higher mosfet switching losses. at high output voltages, the highest efficiency is usually obtained by using a mosfet with a higher r ds(on) and lower q g . the equation above can easily be split into two components (conduction and switching) and entered into a spreadsheet, in order to compare the performance of different mosfets. programming the current limit the peak sense voltage threshold for the ltc3862-2 is 75mv at low duty cycle and with a normalized slope gain of 1.00, and is measured from sense + to sense C . figure 20 illustrates the change in the sense threshold with varying duty cycle and slope gain. a pplica t ions i n f or m a t ion figure 19. normalized power mosfet r ds(on) vs temperature figure 20. maximum sense voltage variation with duty cycle and slope gain junction temperature (c) ?50 t normalized on resistance 1.0 1.5 150 38622 f19 0.5 0 0 50 100 2.0 duty cycle (%) 30 maximum current sense threshold (mv) 60 70 80 55 50 45 40 35 65 75 20 40 60 80 38622 f20 100 100 30 50 70 90 slope = 0.625 slope = 1 slope = 1.66
ltc3862-2 29 38622f for a boost converter where the current limit value is chosen to be 30% higher than the maximum load current, the peak current in the mosfet and sense resistor is: i sw(max) = i r(sense) = 1 n ? 1 + 2 ? ? ? ? ? ? ? 1.3 ? i o(max) 1C d max the sense resistor value is then: r sense = v sense(max) ? n ? 1C d max ( ) 1.3 ? 1 + 2 ? ? ? ? ? i o(max) again, the factor n is the number of phases used, and represents the percentage ripple current in the inductor. the number 1.3 represents the factor by which the cur - rent limit exceeds the maximum load current, i o(max) . for example, if the current limit needs to exceed the maximum load current by 50%, then the 1.3 factor should be replaced with 1.5. the average power dissipated in the sense resistor can easily be calculated as: p r(sense) = 1.3 ? i o(max) n ? 1C d max ( ) ? ? ? ? ? ? 2 ? r sense ? d max this equation assumes no temperature coefficient for the sense resistor. if the resistor chosen has a significant temperature coefficient, then substitute the worst-case high resistance value into the equation. the resistor temperature can be calculated using the equation: t d = t a + p r(sense) ? r th(ja) selecting the output diodes to maximize efficiency, a fast switching diode with low forward drop and low reverse leakage is required. the output diode in a boost converter conducts current during the switch off-time. the peak reverse voltage that the diode must withstand is equal to the regulator output voltage. the average forward current in normal operation is equal to the output current, and the peak current is equal to the peak inductor current: i d(peak) = 1 n ? 1 + 2 ? ? ? ? ? ? ? i o(max) 1C d max although the average diode current is equal to the output current, in very high duty cycle applications (low v in to high v out ) the peak diode current can be several times higher than the average, as shown in figure 21. in this case check the diode manufacturers data sheet to ensure that its peak current rating exceeds the peak current in the equation above. in addition, when calculating the power dissipation in the diode, use the value of the for - ward voltage (v f ) measured at the peak current, not the average output current. excess power will be dissipated in the series resistance of the diode, which would not be accounted for if the average output current and forward voltage were used in the equations. finally, this additional a pplica t ions i n f or m a t ion figure 21. diode current waveform for a high duty cycle application sw node 50v/div inductor current 1a/div diode current 1a/div 1s/div 38622 f21 v in = 12v v out = 72v
ltc3862-2 30 38622f power dissipation is important when deciding on a diode current rating, package type, and method of heat sinking. to a close approximation, the power dissipated by the diode is: p d = i d(peak) ? v f(peak) ? (1 C d max ) the diode junction temperature is: t j = t a + p d ? r th(ja) the r th(ja) to be used in this equation normally includes the r th(jc) for the device plus the thermal resistance from the board to the ambient temperature in the enclosure. once the proper diode has been selected and the circuit performance has been verified, measure the temperature of the power components using a thermal probe or infrared camera over all operating conditions to ensure a good thermal design. finally, remember to keep the diode lead lengths short and to observe proper switch-node layout (see board layout checklist) to avoid excessive ringing and increased dissipation. output capacitor selection contributions of esr (equivalent series resistance), esl (equivalent series inductance) and the bulk capacitance must be considered when choosing the correct combination of output capacitors for a boost converter application. the effects of these three parameters on the output voltage ripple waveform are illustrated in figure 22 for a typical boost converter. the choice of component(s) begins with the maximum acceptable ripple voltage (expressed as a percentage of the output voltage), and how this ripple should be divided between the esr step and the charging/discharging ? v. for the purpose of simplicity we will choose 2% for the maximum output ripple, to be divided equally between the esr step and the charging/discharging ? v. this percentage ripple will change, depending on the requirements of the application, and the equations provided below can easily be modified. one of the key benefits of multi-phase operation is a reduc- tion in the peak current supplied to the output capacitor by the boost diodes. as a result, the esr requirement of the capacitor is relaxed. for a 1% contribution to the total ripple voltage, the esr of the output capacitor can be determined using the following equation: esr cout 0.01 ? v out i d(peak) where: i d(peak) = 1 n ? 1 + 2 ? ? ? ? ? ? ? i o(max) 1C d max the factor n represents the number of phases and the factor represents the percentage inductor ripple current. a pplica t ions i n f or m a t ion figure 22. switching waveforms for a boost converter sw1 100v/div sw2 100v/div v out 100mv/div ac coupled i l1 2a/div i l2 2a/div 1s/div 38622 f22 v in = 24v v out = 72v 350ma load
ltc3862-2 31 38622f for the bulk capacitance, which we assume contributes 1% to the total output ripple, the minimum required ca- pacitance is approximately: c out i o(max) 0.01 ? n ? v out ? f for many designs it will be necessary to use one type of capacitor to obtain the required esr, and another type to satisfy the bulk capacitance. for example, using a low esr ceramic capacitor can minimize the esr step, while an electrolytic capacitor can be used to supply the required bulk c. the voltage rating of the output capacitor must be greater than the maximum output voltage, with sufficient derating to account for the maximum capacitor temperature. because the ripple current in the output capacitor is a square wave, the ripple current requirements for this ca- pacitor depend on the duty cycle, the number of phases and the maximum output current. figure 23 illustrates the normalized output capacitor ripple current as a function of duty cycle. in order to choose a ripple current rating for the output capacitor, first establish the duty cycle range, based on the output voltage and range of input voltage. referring to figure 23, choose the worst-case high nor - malized ripple current, as a percentage of the maximum load current. the output ripple current is divided between the various capacitors connected in parallel at the output voltage. although ceramic capacitors are generally known for low esr (especially x5r and x7r), these capacitors suffer from a relatively high voltage coefficient. therefore, it is not safe to assume that the entire ripple current flows in the ceramic capacitor. aluminum electrolytic capacitors are generally chosen because of their high bulk capacitance, but they have a relatively high esr. as a result, some amount of ripple current will flow in this capacitor. if the ripple current flowing into a capacitor exceeds its rms rating, the capacitor will heat up, reducing its effective capacitance and adversely affecting its reliability. after the output capacitor configuration has been determined using the equations provided, measure the individual ca- pacitor case temperatures in order to verify good thermal performance. input capacitor selection the input capacitor voltage rating in a boost converter should comfortably exceed the maximum input voltage. although ceramic capacitors can be relatively tolerant of overvoltage conditions, aluminum electrolytic capacitors are not. be sure to characterize the input voltage for any possible overvoltage transients that could apply excess stress to the input capacitors. a pplica t ions i n f or m a t ion figure 23. normalized output capacitor ripple current (rms) for a boost converter 0.1 i oripple /i out 0.9 38622 f23 0.3 0.5 0.7 0.8 0.2 0.4 0.6 3.25 3.00 2.75 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0 duty cycle or (1-v in /v out ) 1-phase 2-phase
ltc3862-2 32 38622f figure 24. normalized input peak-to-peak ripple current the value of the input capacitor is a function of the source impedance, and in general, the higher the source impedance, the higher the required input capacitance. the required amount of input capacitance is also greatly affected by the duty cycle. high output current applica- tions that also experience high duty cycles can place great demands on the input supply, both in terms of dc current and ripple current. the input ripple current in a multi-phase boost converter is relatively low (compared with the output ripple current), because this current is continuous and is being divided between two or more inductors. nonetheless, significant stress can be placed on the input capacitor, especially in high duty cycle applications. figure 24 illustrates the normalized input ripple current, where: i norm = v in l ? f a pplica t ions i n f or m a t ion a design example consider the ltc3862-2 application circuit is shown in figure 25a. the output voltage is 72v and the input voltage range is 8.5v to 36v. the maximum output current is 1.5a when the input voltage is 24v and 2a at an input of 32v. below 32v, current limit will linearly reduce the maximum load to 0.5a at 8.5v input voltage (see figure 25b). 1. the duty cycle range (where 1.5a is available at the output) is: d max = v o + v f C v in v o + v f ? ? ? ? ? ? = 72v + 0.5v C 24v 72v + 0.5v ? ? ? ? ? ? = 66.9% d min = 72v + 0.5v C 36v 72v + 0.5v ? ? ? ? ? ? = 50.3% 2. the operating frequency is chosen to be 300khz so the period is 3.33s. from figure 6, the resistor from the freq pin to ground is 45.3k. 3. the minimum on-time for this application operating in ccm is: t on(min) = 1 f ? v o + v f C v in(max) v o + v f ? ? ? ? ? ? = 1 300khz ? 72v + 0.5v C 36v 72v + 0.5v ? ? ? ? ? ? = 1.678s the maximum dc input current is: i in(max) = i o(max) 1C d max = 1.5a 1C 0.669 = 4.5a duty cycle 0 ?i in /i norm 1.00 0.90 0.80 0.60 0.70 0.50 0.40 0.30 0.20 0.10 0 0.8 38622 f24 0.2 0.4 0.6 1.0 1-phase 2-phase
ltc3862-2 33 38622f a pplica t ions i n f or m a t ion figure 25a. a 8.5v to 36v input, 72v/2a output 2-phase boost converter application circuit figure 25b. output current vs input voltage 4. a ripple current of 40% is chosen so the peak current in each inductor is: i in(pk) = 1 n ? 1C 2 ? ? ? ? ? ? ? i o(max) 1C d max = 1 2 ? 1 + 0.4 2 ? ? ? ? ? ? ? 1.5a 1C 0.669 = 2.7a 5. the inductor ripple current is: ? i l = n ? i o(max) 1C d max = 0.4 2 ? 1.5a 1C 0.669 = 0.9a 6. the inductor value is therefore: l = v in(min) ? i l ? f ? d max = 24v 0.9a ? 300khz ? 0.669 = 59.5h 7. for a current limit value 30% higher than the maximum load current: i o(cl) = 1.3 ? i o(max) = 1.3 ? 1.5a = 1.95a the saturation current rating of the inductors must therefore exceed: i l(sat) 1 n ? 1 + 2 ? ? ? ? ? ? ? 1.3 ? i o(max) 1C d max = 1 2 ? 1 + 0.4 2 ? ? ? ? ? ? ? 1.3 ? 1.5a 1C 0.669 = 3.5a sense1 + 3v8 slope blank clkout sync pllfltr phasemode d max 10nf sense1 ? sense2 ? sense2 + run freq ss v in 45.3k 24.9k 150k 10 v in 8.5v to 36v d1 murs320t3h d2 murs320t3h 10 l2 58h pa2050-583 ith sgnd v out 5.62k fb 45.3k 324k 0.1f 1f 1nf 6.8f 50v 0.020 1w q1 hat2267h q2 hat2267h 0.020 1w v out 72v 2a (max) 38622 f25a 47f 100v 47f 100v 6.8f 50v 6.8f 50v 2.2f 100v 6 ltc3862-2 1.5nf 100pf intv cc gate1 gate2 pgnd 4.7f 10nf l1 58h pa2050-583 + + input voltage (v) 0 0.5 0 output load current (a) 1.0 1.5 2.0 2.5 10 20 30 40 38622 f25b
ltc3862-2 34 38622f the inductor value chosen was 57.8h and the part number is pa2050-583, manufactured by pulse engi - neering. this inductor has a saturation current rating of 5a. 8. the power mosfet chosen for this application is a renesas hat2267h. this mosfet has a typical r ds(on) of 13m at v gs = 10v. the bv dss is rated at a minimum of 80v and the maximum continuous drain current is 25a. the typical gate charge is 30nc for a v gs = 10v. last but not least, this mosfet has an absolute maximum avalanche energy rating eas of 30mj, indicating that it is capable of avalanche without catastrophic failure. 9. the total ic quiescent current, ic power dissipation and maximum junction temperature are approximately: i q(tot) = i q + 2 ? q g(tot) ? f = 3ma + 2 ? 30nc ? 300khz = 21ma p diss = 24v ? 21ma = 504mw t j = 70c + 504mw ? 34c/w = 87.1c 10. the inductor ripple current was chosen to be 40% and the maximum load current is 1.5a. for a current limit set at 30% above the maximum load current, the maximum switch and sense resistor currents are: i sw(max) = i r(sense) = 1 n ? 1 + 2 ? ? ? ? ? ? ? 1.3 ? i o(max) 1C d max = 1 2 ? 1 + 0.4 2 ? ? ? ? ? ? ? 1.3 ? 1.5a 1C 0.669 = 3.5a 11. the maximum current sense threshold for the l tc3862 - 2 is 75mv at low duty cycle and a normalized slope gain of 1.0. using figure 20, the maximum sense voltage drops to 68mv at a duty cycle of 70% with a normalized slope gain of 1, so the sense resistor is calculated to be: r sense = v sense(max) i sw(max) = 68mv 3.5a = 19.4m ? for this application a 20m, 1w surface mount resis - tor was used for each phase. 12. the power dissipated in the sense resistors in current limit is: p r(sense) = 1.3 ? i o(max) n ? 1C d max ( ) ? ? ? ? ? ? 2 ? r sense ? d max = 1.3 ? 1.5 2 ? 1C 0.669 ( ) ? ? ? ? ? ? 2 ? 0.020 ? 0.669 = 0.12w 13. the average current in the boost diodes is half the output current (1.5a/2 = 0.75a), but the peak current in each diode is: i d(peak) = 1 n ? 1 + 2 ? ? ? ? ? ? ? i o(max) 1C d max = 1 2 ? 1 + 0.4 2 ? ? ? ? ? ? ? 1.5a 1C 0.669 = 2.7a the diode chosen for this application is the murs320t3h, manufactured by on semiconductor . this surface mount diode has a maximum average forward current of 3a at 140c and a maximum reverse voltage of 200v. the maximum forward voltage drop at 25c is 0.875v and is 0.71v at 150c (the positive tc of the series resistance is compensated by the negative tc of the diode forward voltage). the power dissipated by the diode is approximately: p d = i d(peak) ? v f(peak) ? (1 C d max ) = 2.7a ? 0.71v ? (1 C 0.669) = 0.64w 14. two types of output capacitors are connected in paral - lel for this application; a low esr ceramic capacitor and an aluminum electrolytic for bulk storage. for a 1% contribution to the total ripple voltage, the maximum esr of the composite output capacitance is approximately: esr cout 0.01 ? v out i d(peak) = 0.01 ? 72v 2.7a = 0.267 ? a pplica t ions i n f or m a t ion
ltc3862-2 35 38622f for the bulk capacitance, which we assume contributes 1% to the total output ripple, the minimum required capacitance is approximately: c out i o(max) 0.01 ? n ? v out ? f = 1.5a 0.01 ? 2 ? 72v ? 300khz = 3.45f for this application, in order to obtain both low esr and an adequate ripple current rating (see figure 23), two 47f, 100v aluminum electrolytic capacitors were connected in parallel with six 2.2f, 100v ceramic capacitors. figure 26 illustrates the switching wave- forms for this application circuit. 2. in order to help dissipate the power from the mos- fet s and diodes, keep the ground plane on the layers closest to the power components. use power planes for the mosfets and diodes in order to maximize the heat spreading from these components into the pcb. 3. place all power components in a tight area. this will minimize the size of high current loops. the high di/ dt loops formed by the sense resistor, power mosfet , the boost diode and the output capacitor should be kept as small as possible to avoid emi. 4. orient the input and output capacitors and current sense resistors in a way that minimizes the distance between the pads connected to the ground plane. keep the capacitors for intv cc , 3v8 and v in as close as possible to ltc3862-2. 5. place the intv cc decoupling capacitor as close as possible to the intv cc and pgnd pins, on the same layer as the ic. a low esr (x5r or better) 4.7f to 10f ceramic capacitor should be used. 6. use a local via to ground plane for all pads that connect to the ground. use multiple vias for power components. 7. place the small-signal components away from high frequency switching nodes on the board. the pinout of the ltc3862-2 was carefully designed in order to make component placement easy . all of the power components can be placed on one side of the ic, away from all of the small-signal components. 8. the exposed area on the bottom of the qfn package is internally connected to pgnd; however it should not be used as the main path for high current flow. 9. the mosfets should also be placed on the same layer of the board as the sense resistors. the mosfet source should connect to the sense resistor using a short, wide pcb trace. a pplica t ions i n f or m a t ion figure 26. ltc3862-2 switching waveforms for 72v output boost converter pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the converter: 1. for lower power applications a 2-layer pc board is suf- ficient. however , for higher power levels, a multilayer pc board is recommended. using a solid ground plane and proper component placement under the circuit is the easiest way to ensure that switching noise does not affect the operation. sw1 100v/div sw2 100v/div v out 200mv/div ac coupled i l1 2a/div i l2 2a/div 2s/div 38622 f26 v in = 24v v out = 72v i out = 0.6a
ltc3862-2 36 38622f a pplica t ions i n f or m a t ion 10. the output resistor divider should be located as close as possible to the ic, with the bottom resistor connected between fb and sgnd. the pcb trace connecting the top resistor to the upper terminal of the output capacitor should avoid any high frequency switching nodes. 11. since the inductor acts like a current source in a peak current mode control topology , its placement on the board is less critical than the high di/dt components. 12. the sense + and sense C pcb traces should be routed parallel to one another with minimum spacing in be- tween all the way to the sense resistor. these traces should avoid any high frequency switching nodes in the layout. these pcb traces should also be kelvin- connected to the interior of the sense resistor pads, in order to avoid sensing errors due to parasitic pcb resistance ir drops. 13. if an external rc filter is used between the sense resistor and the sense + and sense C pins, these filter components should be placed as close as possible to the sense + and sense C pins of the ic. ensure that the sense C line is connected to the ground only at the point where the current sense resistor is grounded. 14. keep the mosfet drain nodes (sw1, sw2) away from sensitive small-signal nodes, especially from the opposite channels current-sensing signals. the sw nodes can have slew rates in excess of 1v/ns relative to ground and should therefore be kept on the output side of the ltc3862-2. 15. check the stress on the power mosfets by indepen - dently measuring the drain-to-source voltages directly across the devices terminals. beware of inductive ringing that could exceed the maximum voltage rating of the mosfet. if this ringing cannot be avoided and exceeds the maximum rating of the device, choose a higher voltage rated mosfet or consider using a snubber. 16. when synchronizing the ltc3862-2 to an external clock, use a low impedance source such as a logic gate to drive the sync pin and keep the lead as short as possible.
ltc3862-2 37 38622f typical a pplica t ions a 6v to 60v input, 12v/6a output 2-phase sepic application circuit start-up load step efficiency run 5v/div v in = 12v v out = 12v r l = 12 v out 5v/div i l1a + i l1b 10a/div i l2a + i l2b 10a/div 500s/div 38622 ta04b v in = 12v v out = 12v ?i out = 1a to 6a i out 5a/div v out 1v/div ac-coupled 500s/div 38622 ta04c load current (ma) efficiency (%) 38622 ta01b 91 86 87 88 89 90 80 82 81 83 84 85 100 1000 10000 v out = 12v v in = 6v v in = 12v v in = 14v r osc 66.5k c ss 10nf ltc3862-2 d max slope blank phasemode freq ss ith fb sgnd clkout sync pllfltr v in run 3v8 intv cc gate1 sense1 + sense1 ? pgnd gate2 nc sense2 + sense2 ? 38621 ta02a r1 12.4k r2 113k r c1 6.34k c c2 100pf c c1 10nf v out c u1 1f r11 249k c3 10nf c1 1nf c2 4.7f r3 845k r6 0.004 q1 bsc060n10ns3g 7,8,9 4,5,6 10,11,12 1,2,3 q4 bsc060n10ns3g r8 0.004 r4 10 ?? ?? 10 c4 10nf l2 vp5-0083-r d2 v8p10 cd4-6 3 2.2f 100v cd1-3 3 2.2f 100v d1 v8p10 l1 vp5-0083-r 7,8,9 4,5,6 10,11,12 1,2,3 c out1-6 6 6.8f 50v c out 7-8 2 150f 16v + c in1-5 5 2.2f 100v v out v in 6v to 60v v out 12v at 6a r27 22k q5 pmst5550 3v8 q2 pmst5550 r5 10k r9 220k r13 10k r12 56k d3 pbz6.8b q3 pbss9110t d4 bas516
ltc3862-2 38 38622f t ypical applica t ions a 6v to 32v input, 80v/7a output 2-phase boost converter application circuit start-up efficiency vs output current run 5v/div v in = 12v v out = 80v r l = 100 v out 20v/div i l1 10a/div i l2 10a/div 2ms/div 38622 ta03b load current (ma) efficiency (%) 38622 ta03c 97 87 89 91 93 95 77 79 81 83 85 10 1000 100 10000 v in = 6v v in = 9v v in = 12v v in = 24v v out = 80v sense1 + 3v8 slope blank clkout sync pllfltr phasemode d max 10nf sense1 ? sense2 ? sense2 + run freq ss v in 110k 24.9k 100k 10 v in 6v to 32v d1 v8p10 d2 v8p10 10 l2 16h pqa2050-16 ith sgnd v out 12.4k fb 12k 796k 0.1f 1f 1nf 6.8f, 50v 3.3m q1 bsc06n10 q2 bsc06n10 3.3m v out 80v 7a (max) 3862 ta03a 100f 100v 6.8f, 50v 6.8f, 50v 2.2f 100v 5 ltc3862-2 10nf 220pf intv cc gate1 gate2 pgnd 4.7f 10nf l1 16h pqa2050-16 + 100f 100v +
ltc3862-2 39 38622f t ypical applica t ion s a 24v input, 48v/6a output 2-phase boost converter application circuit start-up load step efficiency sense1 + 3v8 slope blank clkout sync pllfltr phasemode d max 10nf sense1 ? sense2 ? sense2 + run freq ss v in 45.3k 24.9k 150k 10 v in 8.5v to 36v d1 30bq060 d2 30bq060 10 l2 19h pa2050-193 ith sgnd v out 7.87k fb 30.1k 301k 0.1f 1f 1nf 22f 25v 0.005 1w q1 hat2279h q2 hat2279h 0.005 1w v out 48v 6a (max) 3862 ta04a 100f 35v 22f 25v 22f 25v 10f 50v ltc3862-2 4.7nf 100pf intv cc gate1 gate2 pgnd 4.7f 10nf l1 19h pa2050-193 + 100f 35v + 10f 50v 10f 50v 10f 50v run 5v/div v in = 24v v out = 48v r l = 100 v out 50v/div i l1 5a/div i l2 5a/div 1ms/div 38622 ta04b i out 5a/div v in = 24v v out = 48v ?i out = 1a to 5a v out 1v/div ac-coupled i l1 5a/div i l2 5a/div 500s/div 38622 ta04c load current (ma) efficiency (%) power loss (mw) 100 96 92 38622 ta04d 84 10000 1000 88 10000 100 1000 v in = 24v v out = 48v efficiency power loss
ltc3862-2 40 38622f a 24v input, 107v/1.5a output 2-phase boost converter application circuit start-up load step efficiency t ypical applica t ion s sense1 + 3v8 slope blank clkout sync pllfltr phasemode d max 10nf sense1 ? sense2 ? sense2 + run freq ss v in 68.1k 24.9k 150k 10 v in 8.5v to 36v d1 pds4150 d2 pds4150 10 l2 58h ith sgnd v out 6.65k fb 43.5k 576k 0.1f 1f 1nf 22f 25v 0.010 1w q1 si7430dp q2 si743odp 0.010 1w v out 107v 1.5a (max) 38622 ta05a 100f 150v 22f 25v 22f 25v 8 1f 250v ltc3862-2 2200pf 47pf intv cc gate1 gate2 pgnd 4.7f 10nf l1 58h + l1, l2: champs technologies hrpqa2050-57 pulse engineering pa2050-583 run 5v/div v in = 24v v out = 107v i load = 400ma v out 50v/div i l1 2a/div i l2 2a/div 2ms/div 38622 ta05b i out 2a/div v in = 24v v out = 107v i load = 500ma to 1.5a v out 1v/div ac-coupled i l1 2a/div i l2 2a/div 500s/div 38622 ta05c load current (ma) efficiency (%) power loss (mw) 100 96 92 38622 ta05d 76 84 80 100000 1000 10000 88 10000 100 1000 v in = 24v v out = 107v efficiency power loss
ltc3862-2 41 38622f p ackage descrip t ion fe package 24-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation aa fe24 (aa) tssop 0208 rev ? 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref recommended solder pad layout 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 11 12 14 13 7.70 ? 7.90* (.303 ? .311) 3.25 (.128) 2.74 (.108) 2021222324 19 18 17 16 15 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 3.25 (.128) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
ltc3862-2 42 38622f gn package 24-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) p ackage descrip t ion .337 ? .344* (8.560 ? 8.738) gn24 (ssop) 0204 1 2 3 4 5 6 7 8 9 10 11 12 .229 ? .244 (5.817 ? 6.198) .150 ? .157** (3.810 ? 3.988) 161718192021222324 15 14 13 .016 ? .050 (0.406 ? 1.270) .015 .004 (0.38 0.10) 45 0 ? 8 typ .0075 ? .0098 (0.19 ? 0.25) .0532 ? .0688 (1.35 ? 1.75) .008 ? .012 (0.203 ? 0.305) typ .004 ? .0098 (0.102 ? 0.249) .0250 (0.635) bsc .033 (0.838) ref .254 min recommended solder pad layout .150 ? .165 .0250 bsc .0165 .0015 .045 .005 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
ltc3862-2 43 38622f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion uh package 24-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1747 rev a) please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 5.00 0.10 5.00 0.10 note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.55 0.10 23 1 2 24 bottom view?exposed pad 3.25 ref 3.20 0.10 3.20 0.10 0.75 0.05 r = 0.150 typ 0.30 0.05 (uh24) qfn 0708 rev a 0.65 bsc 0.200 ref 0.00 ? 0.05 0.75 0.05 3.25 ref 3.90 0.05 5.40 0.05 0.30 0.05 package outline 0.65 bsc recommended solder pad layout apply solder mask to areas that are not soldered pin 1 notch r = 0.30 typ or 0.35 45 chamfer r = 0.05 typ 3.20 0.05 3.20 0.05 uh package 24-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1747 rev a)
ltc3862-2 44 38622f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2012 lt 0312 ? printed in usa r ela t e d p ar t s part number description comments ltc3788/ ltc3788-1 dual output, multiphase synchronous step-up controller 4.5v (down to 2.5v after start-up) v in 38v, v out up to 60v, 50khz to 900khz fixed frequency, 5mm 5mm qfn-32, ssop-28 ltc3787/ ltc3787-1 single output, dual channel multiphase synchronous step-up controller 4.5v (down to 2.5v after start-up) v in 38v, v out up to 60v, 50khz to 900khz fixed frequency, 4mm 5mm qfn-28, ssop-28 ltc3786 low i q synchronous step-up controller 4.5v (down to 2.5v after start-up) v in 38v, v out up to 60v, 50khz to 900khz fixed frequency, 3mm 3mm qfn-32, msop-16e ltc3862/ ltc3862-1 multiphase, dual channel single output current mode step-up dc/dc controller 4v v in 36v, 5v or 10v gate drive, 75khz to 500khz fixed operating frequency, ssop-24, tssop-24, 5mm 5mm qfn-24 ltc3859a low i q , triple output buck/buck/boost synchronous dc/dc controller all outputs remain in regulation through cold crank, 4.5v (down to 2.5v after start-up) v in 38v, v out(bucks) up to 24v, v out(boost) up to 60v, i q = 55a LTC3789 high efficiency synchronous 4-switch buck-boost dc/dc controller 4v v in 38v, 0.8v v out 38v, 4mm 5mm qfn-28, ssop-28 typical a pplica t ion a 6v to 60v, 12v/6a output 2-phase sepic application circuit r osc 66.5k c ss 10nf ltc3862-2 d max slope blank phasemode freq ss ith fb sgnd clkout sync pllfltr v in run 3v8 intv cc gate1 sense1 + sense1 ? pgnd gate2 nc sense2 + sense2 ? 38621 ta06 r1 12.4k r2 113k r c1 6.34k c c2 100pf c c1 10nf v out c u1 1f r11 249k c3 10nf c1 1nf c2 4.7f r3 845k r6 0.004 q1 bsc060n10ns3g 7,8,9 4,5,6 10,11,12 1,2,3 q4 bsc060n10ns3g r8 0.004 r4 10 ?? ?? 10 c4 10nf l2 vp5-0083-r d2 v8p10 cd4-6 3 2.2f 100v cd1-3 3 2.2f 100v d1 v8p10 l1 vp5-0083-r 7,8,9 4,5,6 10,11,12 1,2,3 c out1-6 6 6.8f 50v c out 7-8 2 150f 16v + c in1-5 5 2.2f 100v v out v in 6v to 60v v out 12v at 6a r27 22k q5 pmst5550 3v8 q2 pmst5550 r5 10k r9 220k r13 10k r12 56k d3 pbz6.8b q3 pbss9110t d4 bas516

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